Cdma Coded Wrapper-based System Bus

The recent development of Field Programmable Gate Array (FPGA) System-on-Chip (SoC) architectures, with coarse-grain processors, embedded memories and Intellectual Property (IP) cores, offers high performance for computing power as well as opportunities for rapid system prototyping. These platforms require high-performance onand off-chip communication architectures for efficient and reliable inter-processor data transfer. By increasing the number of IP cores that are embedded in a SoC design, as well as the number of VLSI circuits that are installed in circuit boards, the problem of interconnection becomes more challenge. In this paper, we propose an efficient technique for realization of onand off-chip system bus based on wrapper technology and CDMA techniques, in order to achieve efficient data transfer among IP cores in SoC and among chips on circuit boards. The main benefits of using this technique related to decreasing the number of wires on system bus in average for 50 %, while the main disadvantage deals with increasing the latency of Read and Write processor cycles.